By Douglas E. Ott
A Designer's consultant to VHDL Synthesis is meant for either layout engineers who are looking to use VHDL-based common sense synthesis ASICs and for managers who have to achieve a pragmatic figuring out of the problems excited about utilizing this expertise. The emphasis is positioned extra on sensible functions of VHDL and synthesis in line with real studies, instead of on a extra theoretical method of the language.
VHDL and good judgment synthesis instruments supply very robust functions for ASIC layout, yet also are very advanced and symbolize a thorough departure from conventional layout equipment. this case has made it tough to start in utilizing this know-how for either designers and administration, on the grounds that a huge studying attempt and `culture' swap is needed. A Designer's consultant to VHDL Synthesis has been written to aid layout engineers and different pros effectively make the transition to a layout technique according to VHDL and log synthesis rather than the extra conventional schematic dependent process. whereas there are many texts at the VHDL language and its use in simulation, little has been written from a designer's point of view on the best way to use VHDL and good judgment synthesis to layout actual ASIC structures. the cloth during this ebook is predicated on event won in effectively utilizing those suggestions for ASIC layout and is based seriously on reasonable examples to illustrate the rules concerned.
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Extra info for A Designer’s Guide to VHDL Synthesis
Design Management: The process of designing larger and more complex ASICs within schedule constraints may require a team of designers working on a single ASIC. Similarly, on a large project several ASIC designers will often work under the guidance of a project leader whose job is to coordinate and review the individual designs. As an aid to maintaining good design practices and documentation, the VHDL language contains many of the structured design capabilities that can be found in most software programming languages.
Also signals such as clocks may not be specifically used, and data busses are often treated as integer or real values without any specific number of bits. As an example, the system's behavior may be to wait for a certain type of message to arrive on a data bus and, when it occurs, to set some system parameters and output signals to desired states and then Wait for 80 microseconds. Exactly how to wait for 80 usee is part of the detailed hardware implementation and is not needed at this level of abstraction, nor are the details of how the outputs or system states are set.
There are many types of ASIC testability approaches that can be used, ranging from the use of full scan or partial scan logic to less formal or Chapter 2 27 "ad hoc" approaches, such as providing additional output multiplexers for increased observability and input signals for improved controllability. Decisions on whether to use JTAG or other boundary scan approaches for board or system level testing, whether to incorporate built in self test (or BIST) mechanisms, and any other special testability requirements should also be considered at this point.