Adaptable Embedded Systems by Antonio Carlos Schneider Beck, Carlos Arthur Lang Lisbôa,

By Antonio Carlos Schneider Beck, Carlos Arthur Lang Lisbôa, Luigi Carro

As embedded platforms develop into extra advanced, designers face a couple of demanding situations at diverse degrees: they should advance functionality, whereas preserving power intake as little as attainable, they should reuse existent software program code, and while they should benefit from the additional common sense on hand within the chip, represented via a number of processors operating jointly. This publication describes a number of suggestions to accomplish such various and interrelated ambitions, by means of adaptability. assurance contains reconfigurable structures, dynamic optimization ideas equivalent to binary translation and hint reuse, new reminiscence architectures together with homogeneous and heterogeneous multiprocessor structures, verbal exchange concerns and NOCs, fault tolerance opposed to fabrication defects and gentle error, and eventually, how you can mix a number of of those thoughts jointly to accomplish greater degrees of functionality and flexibility. The dialogue additionally comprises how one can hire really expert software program to enhance this new adaptive process, and the way this new form of software program has to be designed and programmed.

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Moreover, more control circuitry is necessary (to configure the ALUs). On the other hand, the circuit is more flexible: any arithmetic and logic operation can be performed. By extending this concept even more, it is possible to add ALUs working in parallel, and multiplexers to route the values between them (Fig. 5b). Again, the critical path increases, even more control hardware is necessary, but there is even more flexibility, besides the possibility of executing operations in parallel. The main principle remains the same, though: to group instructions to be executed in a more efficient manner, but now with some flexibility.

SHA RawAudio E GSM Enc. RawAudio D GSM Dec. CRC32 Bitcount 0 Fig. 1 Instruction per branch rate on reconfigurable logic, we discuss reconfiguration and execution times, and the growing number of applications being executed at the same time on a system. 1 Heterogeneous Behavior of the Applications In this study, a subset of the MiBench Benchmark Suite [4] that represents a complete set of diverse algorithm behaviors is used. g. SPEC2000 [7]. We have evaluated the following 18 applications: Quicksort, Susan Corners/Edges/Smoothing, Jpeg Encoder/Decoder, Dijkstra, Patricia, StringSearch, Rinjdael Encode/Decode, SHA, Raw Audio Coder/Decoder, GSM Coder/Decoder, Bitcount and CRC32.

Again, the critical path increases, even more control hardware is necessary, but there is even more flexibility, besides the possibility of executing operations in parallel. The main principle remains the same, though: to group instructions to be executed in a more efficient manner, but now with some flexibility. This is, in fact, an example of a coarse-grained reconfigurable array, which will be presented in more details later in this chapter. 6 graphically shows the difference between using reconfigurable logic and a traditional parallel architecture to execute instructions.

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