By Kirk Zurell
Wanting to move your c program languageperiod abilities to the 8-bit microcontroller embedded setting? This publication gets you up and working quick with transparent causes of the typical architectural components of such a lot 8-bit microcontrollers and the embedded-specific de wake up and operating quick with this transparent presentation of 8-bit MCU improvement rules and demonstration venture, whole with schematics, a elements record, and pattern code. study the main points of device-specific improvement -- from initial software program layout to implementation of a operating purchaser product.
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The following are some sample port configurations. • The COP8SAA7 has four bidirectional 8-bit I/O ports called C, G, L, and F, in which each bit can be either input, output, or tristate. The programming interface for each has an associated configuration register (determines how the port behaves) and data register (accepts data for or presents data from the port). • The Motorola MC68HC705C8 has three 8-bit ports called A, B, and C that can be either inputs or outputs depending on the value of the DDR.
Wish-list items to ask for include the following. A Built-in Debug Interface Another method of field-programmability would also suffice. When a device must be installed, customized, or repaired on site, a Flash-RAM part makes more sense than an EEPROM or ROM device. ROM Code Protection Embedded processors often provide protection against casual examination of your ROM code. A configuration bit inhibits reading of ROM through the programming interface. While there are sev-Page 7 eral exploits against this protection, only a determined opponent will succeed in reading your programming.
Part of this dilemma will be resolved in part selection: some processor variants do not include interrupts at all. Other choices include explicit Page 10 support for interrupt-driven keypads, or timers that generate interrupts upon timeout. A serious facet of an interrupt-based solution is the protocol for communication between the interrupts and main-line code. Since interrupts and main line are as independent as possible (an interrupt may occur during any main-line instruction), race conditions are one consequence.