An Artificial Intelligence Approach to VLSI Routing by R. Joobbani

By R. Joobbani

Routing of VLSI chips is a vital, time eating, and tough challenge. the trouble of the matter is attributed to the big variety of usually conflicting elements that have an effect on the routing caliber. conventional innovations have approached routing through ignoring a few of these components and enforcing pointless constraints as a way to make routing tractable. as well as the imposition of those regulations, which simplify the issues to a point yet while decrease the routing caliber, conventional techniques use brute strength. they typically rework the matter into mathematical or graph difficulties and fully forget about the categorical wisdom concerning the routing activity that may drastically support the answer. This thesis overcomes a number of the above difficulties and offers a process that plays routing with reference to what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this region, it doesn't impose pointless constraints, it considers the entire various factors that impact the routing caliber, and most significantly it permits consistent consumer interplay in the course of the routing procedure. to accomplish the above, this thesis provides heritage approximately a few consultant recommendations for routing and summarizes their features. It then reviews intimately the various elements (such as minimal sector, variety of vias, twine size, etc.) that impact the routing caliber, and different standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.

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Extra resources for An Artificial Intelligence Approach to VLSI Routing

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Merging is a combinatorial problem. To reduce the complexity we have employed two special techniques: 1. Rather than starting from one side of the channel and merge one net at a time, start from both sides of the channel and proceed to the middle of the channel. An example with 8 nets shows the effectiveness of this technique. As Figure 3·15 shows merging from one side (Figure 3·15(a» needs 6 steps, whereas merging from both sides (Figure 3·15(b» needs only 4 steps. This technique in combination with the next technique reduces the complexity considerably.

The right subnet has 4 pins on the top and two pins on the bottom (one pin is the vertical part that connects to the left subnet and the other is the rightmost bottom pin). To avoid the above problems, WEAVER uses the rectilinear Steiner tree to find the best routing pattern for a net and then applies the wire length concept for each segment of the net appropriately. 3 2 (a) 2 3 (b) Figu re 3·6: Suboptimality of considering the wire length for single net, (a) suboptimal routing, (b) optimal routing.

I } (g) or { ~. 1. b. c. d. g. h } Figu re3·12: Step by step calculation of MRST for a net. As was mentioned in the worst case the algorithm is exponential in m but this case rarely occurs and when it does occur it is for one net in the routing area and it pays off because all the other nets can be calculated in linear time. The worst case is shown in Figure 3-13. It is the case where a net has pins on all four corners of the channel such that no reduction rule applies and has at least one pin on top/bottom and one pin on the right/left side of the 35 routing area such that the number of possible trees to be generated is relatively large.

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